CountingDaq 250130

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Meeting information

 Meeting time:  11:00am Eastern
 Location at JLab:  CC F226
 
 Zoom connection information is sent out by email; please reach out to Paul if you don't have the current link.

Agenda

• Activity updates
  • Some counting DAQ updates were presented in the integrating DAQ meetings on December 13 and January 10.
• General discussion

Minutes

Recording on Zoom:

Participants: R. Michaels, P. King, S. Malace, C. Cuevas, B. Moffit, A. Sen, D. Armstrong, B. Blaikie, H. Liu, Z. Ji, R. Conaway, J. Datta, S. Regmi, J. Shirk, P. Gautam, D. McNulty, C. Ghosh, P. Souder, S. Chatterjee

• Status of the W&M test stand
  • The system is in use. They have software control of the HV and LV crates and are taking data
  • Transitioning to being able to use the VTP triggering will likely require changing the CODA version. Arindam and Paul are doing some tests of changing the CODA version on the integrating DAQ test stand now, to work out the issues before taking down the W&M DAQ
  • When we're ready we'll arrange a time with the detector group to do it
• Pion detector test stand
  • Arindam and Zhongling are basically ready to go, but need a pulser. Simona may be able to have one loaned in for it, and she and Paul will discuss if we can get one of our own
  • Will also be trying to recruit the Hall A/C postdoc to help with the pion det. tests.
• ESB test stand
  • Simona has two FADCs, one for each crate
  • Simona and Hanjie will work together to set up CODA for the ESB
• Some discussion on the VTP trigger development
  • We only need a sector-based coincidence between the scintillators, and coincidences between other types of detectors would be just at the "ring" level.
  • David and Simona will also have a side discussion to
  • Simona has a proposed FADC map in which all the channels of a particular ring would be grouped together, and then marching through the detector array. I.e. ring 1 would be the first 1.75 FADCs, then ring 2 would start in the 2nd and fill through the 3rd and 4th, and so on. Paul & Simona will reach out to Michael to see if he has any preference.
• FADCv3 testing: a few modules have had assembly issue and are going back to the vendor
  • The full crate testing is rolling through the modules. Chris thinks they would probably start to release boards next week
  • Chris recommends storing and moving the modules in the special antistatic crates that they bought
  • The firmware that is available is the Hall D version, which doesn't support the VTP triggering
    • Chris will need to follow up with Ben about the development for the firmware design that supports the VTP triggering
      • Once the modules are available, the ESB test stand would be an excellent place to do further tests and provide feedback to FEG
  • Simona asks if we need to do the testing in ESB before the project finishes "Test FADCs"; we think that no, the testing done by FEG should be sufficient to declare them working.
• Chris asks when the final integrating ADC will be available to test-fit the chassis
  • Hopefully soon; depends on getting the modules back from the vendor after changing the SoM socket
  • But they will send a chassis to Dustin; he has a rev1 ADC, so some minor changes
• Chandan is working in the testlab GEM daq now to upgrade from SSP to VTP