IntegrationDaq 210129

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Revision as of 14:57, 28 January 2021 by Pking (Talk | contribs) (Agenda)

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Meeting information

 Meeting time:  3:30pm Eastern
 
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Agenda

  • Activity updates
  • Follow-up from the Jan 15 discussion of running the integrator data from the FPGA instead of through a ROC on the SoC
    • Reminder: Production data rate from each integrating ADC module is ~4MB/s. The diagnostic mode data rate (without deadtime) is ~34MB/s/channel --> ~544MB/s (~4.3Gb/s) for all channels in the module; we do not need to be able to maintain this rate deadtime-free.
  • General discussion

Minutes

Participants: