IntegrationDaq 210129

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Meeting information

 Meeting time:  3:30pm Eastern
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  • Activity updates
  • Follow-up from the Jan 15 discussion of running the integrator data from the FPGA instead of through a ROC on the SoC
    • Reminder: Production data rate from each integrating ADC module is ~4MB/s. The diagnostic mode full data rate is ~34MB/s/channel giving ~544MB/s (~4.3Gb/s) for all channels in the module.
    • Reminder: The SOM is the Mercury+ XU8, and the evaluation board that is currently used for testing is the Mercury+ PE1
  • General discussion


Participants: Robert M., Bryan, Bryerton, Brynne, Chris C., Daryl, Jie, Michael, William, Paul K., Jim F.

  • Activity updates
    • Michael has set up the test board like it was in Mainz, ready for further testing
    • Jie has a new switching base design that will be used for testing
    • Bryerton is working on another project, will be back to the ADC project in Feb.
    • Bryan has a ZCU106 eval board. He has Centos7 running on the UltraScale
      • This will be used by William to develop the TI interface, and for David to port the CODA ROC
  • Follow up from the Jan 15 discussion
    • Bryan had been a little mistaken about what Ben is doing for the "hardware readout". What is being developed is a software ROC that would be running on the VTP.
    • Bryan summarizes what he thinks is the way forward:
      • Bryerton would continue to develop the ADC readout without using CODA. In this development effort, he will develop a standalone readout system that runs on the SOM in Petalinux
      • Bryan et al. will develop the CODA ROC to run on the SOM.
      • Bryan will use the memory map that is developed by Bryerton to generate the CODA interface
      • William will develop the TI interface firmware module and provide that
        • The TI interface connection has been included in the full board design
  • General discussion
    • Michael proposes a design review in the summer, with the first full prototype in fall or winter
    • The full scale input for the ADC channel right now is +/-2.048 volts.
      • The stripline BPM voltages are perhaps a dynamic range of 1-5V.
        • Paul will write up a summary of what the BPM signal levels are. Once we know that, there will need to be a discussion of what the front-end needs to accept.
          • Daryl also asks for not just voltage levels but the bandwidth expectations for other signals.
        • Remember that the ADC inputs are differential, and the BPM signals are single ended, so we'd need some adaptation of those signals anyway, so we might just have an interface that adapts both the cable and signal levels to match the ADC front end
    • Let's meet again on 12 February