IntegrationDaq 210115

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Meeting information

 Meeting time:  3:30pm Eastern
 
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Agenda

• General discussion

Minutes

Participants: Bryan, Bryerton, Brynne, Daryl, Jie, Michael G., Bob M., Paul K.

• Bryerton is looking into some improvements suggested by Michael to improve the data rate in the current test system; he will likely not get to it before February. This would be to get the sampling rate back up to 15MHz and get higher data transport rate
• Michael: Objectives over the next few months
  • They have a new PMT base prototype that includes the gain switching; with a new preamp and the improvements to the ADC they'd plan to test the filter rolloff and the ADC linearity tests
  • Using that with a PMT+quartz+UV LED can test detector linearity too
  • Evaluation of the full board design by Daryl & Bryerton
  • In summer or fall, plan to have a full review of the design including both JLab and Mainz experts
• Jie: Updating some documents on the full board design; expect to give this to D&B in a few weeks for them to start to review the design
• Bryan: The ROC has been ported to the 32-bit ARM processor
• Bryerton asks if the board should be controlled by a pub/sub interface that would communicate with CODA processes but the integrating ADC would not have a ROC
  • This would be to dumb-down what the board is asked to do
  • The board would still take a trigger and it would then stream the data out. Bryan says that this is similar to what JLab is developing for the VTPs.
  • The full board design has two QSFP connectors, one for the TI interface and one for data transport. There are also two 1G ethernet links.
  • Bryan says that the VTP project (Ben Raydo and Dave Abbott) should have results in the next few months and this is needed for SBS.
  • Bryan will keep up to date with Ben and will report back.
  • We should ask William to join our next meeting
  • Daryl asks if the data transport QSFP could use UDP protocol. Bryan says that's what is used for CODA.
  • Michael asks what the role of the extra two 1G ethernet links are for; Jie reminds him that they were intended for slow control, or for use on the bench
  • Daryl and Bryerton discuss if the QSFP ports should go through the SOC or just to the FPGA fabric. This can likely be changed in firmware without having to change the board design.
  • In order to support 10G, Bryerton says that we might need to buy extra IP from Xilinx
• Bryan will report back to us in two weeks about the VTP project
• We'll keep this meeting time and continue every other week, so the next meeting would be 29 January.