IntegrationDaq 240531

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Meeting information

 Meeting time:  1:00pm Eastern
 
 Zoom connection information is sent out by email; please reach out to Paul if you don't have the current link.

Agenda

• Activity updates
• General discussion

Open Issues to be followed up later

1. Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
2. Draft timing diagram: DocDB 790
3. Michael, Bob, Brynne, and Paul should put together a list of the integrator running modes we would like to have available

Minutes

Recording at zoomgov: https://jlab-org.zoomgov.com/rec/share/YASZM69gbRaKLi5zBES8Kup3uberBBQRIbCH3PV16ralRKS6pxMyYozjkiYGTcdx.htn0svrrUh20ahUc?startTime=1717174444000

Participants: R. Michaels, P. King, C. Cuevas, A. Sen, B. Blaikie, K. Dehmelt, D. Bishop, B. Moffit, W. Gu, Z. Ji, J. Pan, S. Regmi, B. Shaw

• Discussion of how the TI integrate signal would be handled
  • Right now he isn't using the TI to generate a trigger signal yet
  • How deep could a look back be? Right now there isn't one.
    • Maybe the better way to handle the "lookback" would be to adjust the trigger time to be earlier
  • We would want an option for the number of blocks, and for the number of samples per block
  • Markers for the streaming mode: one bit to indicate that we are in the integration period, a second bit to indicate if we are in an even or odd subblock
  • While integrating (# of blocks)*(# of samples) the FPGA will present a busy signal to the TI block.
    • William will follow up on how to communicate the busy to the TI block
• Question on if we should use SFP+ or stay with the QSFP
  • Would we ever use more than one link out of the QSFP? Maybe not, but Michael might have other ideas
  • Currently the CPU can send 1G of data, over either the copper or the fiber. This would be for the integration data.
  • We think it is better to keep the QSFP on the module, and use a QFSP-to-SFP+ adapter to go to a SFP+ switch
• Question on the SD card holder
  • Bryerton has found a vertical SD card holder that he's sent to Daryl
• Question about how the clocks would be synchronized
  • Right now the ADC sample clock is generated using a "divide-by-17" counter on the 250MHz trigger, and it is free-running (so two modules might not be measuring at the same moment)
  • We think it will be best to use the TI clock-sync to reset the "divide-by-17" counter, so that all modules have the same phase of the "divide-by-17". This gets sent by the TI at the beginning of a data run.
• Bryan has the two ADC modules and is getting set up
  • The 250 MHz clock is getting down to the FPGA
  • He doesn't see the triggers and doesn't see the sync reset. This seems to be different from the version that they had been using in March
    • These would be seen in registers within the TI block. He'll follow up with Bryerton