IntegrationDaq 231215

Back to Main Page >> Data Acquisition Meetings >> Integrating mode DAQ meetings

previous meeting << >> following meeting

Meeting information

 Meeting time:  1:00pm Eastern
 
 Zoom connection information is sent out by email; please reach out to Paul if you don't have the current link.

Agenda

• Activity updates
• General discussion

Open Issues to be followed up later

1. Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
2. Draft timing diagram: DocDB 790
3. Michael, Bob, Brynne, and Paul should put together a list of the integrator running modes we would like to have available

Minutes

Recording at zoomgov: [1]

Participants: R. Michaels, R. Conaway, B. Blaikie, M. Gericke, P. King, W. Gu, B. Moffit, B. Shaw, J. Pan, S. Chatterjee, D. Bishop, S. Regmi, D. McNulty, C. Cuevas, H. Liu

• Michael received the first seven of the prototype boards earlier this week, and is about to start testing them. The last one is due from the vendor soon.
• Michael has circulated a draft of the firmware specification document
• Bryerton doesn't have an update yet on the number of samples we could take from 16ch of one helicity window for the timing alignment
• Bryan doesn't have an update but has two questions
  • He asked for a description of the back panel connections and how they work with the current firmware
  • He also asks if the ADC can trigger from the TI signal: Bryerton says that right now only the external TTL is used for the trigger, and defining how the TI will trigger the integrating-mode readout is part of what we need from the firmware specification document
• Discussion of LVDS connections on the module and what signals we might want to have to be routed to them.
  • There are 2 TTL inputs (minimum width 10 ns), 2 NIM inputs, and 4 LVDS signals that can be either input or output (probably can go up to 200-300 MHz)
  • The NIM inputs in the revision 0 boards are missing emitter resistors, so the inputs won't work without having a resistor added
  • We should think about what signals it would be useful to have available as outputs
• There is a incorrect resistor in the PoE circuit on the revision 0 boards, it should have been a 1kohm resistor but due to an incorrect part number the resistor placed was a 53ohm. Daryl and Jie will follow up about what needs to be fixed. This has been fixed in the newer prototypes
• Jie has identified a different DC-DC converter for the base+amp assemblies which is supposed to be radiation-hard to 100krad which had been used by NASA. She's reaching out to the manufacturer to see if we would be able to get these.
• I ask about the ePAS system: Chris thinks that the integration module chassis will be a low enough hazard that we won't need to worry about it yet, until we start to get set up for the hall
• Chris asks about the integrating ADC chassis. Michael will plan to buy them from the vendor which JLab had worked with to make the first one.
• I mention that Arindam Sen is joining the OU group and will be stationed at the lab starting next week.
  • I would plan on having him working with the integrating ADC once we have the CODA libraries to get used to how to work with it
  • Bob says that he had talked with Walt Akers about getting another lab space that we could set up another test stand
• I suggest that we might try to swap the parity DAQ crate in the counting house for one of our VXS crates so that we could use the new helicity decoder module in parallel with the existing charge feedback DAQ system.
  • Bob and I need to discuss this offline
• The next meeting will be 12 January (no meeting on 29 December)
• I ask if anyone is aware of conflicts with keeping the DAQ meetings at 1pm on Fridays
  • Michael is unsure of his schedule right now and will follow up by email.