IntegrationDaq 220812

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Meeting information

 Meeting time:  12:00pm Eastern
 
 Zoom connection information
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 https://jlab-org.zoomgov.com/j/1603800887?pwd=aXVmSnN6aWZWN3RBdXB4RUhGckZJdz09
 
 Meeting ID: 160 380 0887
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Agenda

• Activity updates
  • Possible chassis design by Armen (JLab)
• General discussion

Open Issues to be followed up later

1. Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
2. Draft timing diagram: DocDB 790
3. Michael, Bob, Brynne, and Paul should put together a list of the integrator running modes we would like to have available

Minutes

Recording at zoomgov: [1]

Participants: W. Gu, P. King, B. Moffit, R. Michaels, B. Blaikie, B. Shaw, J. Pan, C. Zorn, D. McNulty, M. Gericke

• Activity updates
  • Discussion of initial chassis design by Armen
    • TRIUMF and Manitoba have not yet done design work on the chassis
    • The airflow is side-to-side
    • The chassis is 2U. In my rackmount estimates, I'd assumed 1U plus 1U for airflow, so a 2U side-to-side chassis would be about the same rack footprint as I had estimated
    • It uses the present size of the board, which is why it isn't just an off-the-shelf rackmount box. Michael and Jie say that the board could be made slightly smaller without any layout changes (or with very minimal changes); but right now we don't think that is needed
    • We can talk with Chris about the airflow. We could also do a CFD to see what the cooling might be. We can also just try the prototype and see how it performs
    • Bryerton suggests putting some venting above the CPU fan, if that is the only fan in the box
  • Bob expects to be able to bring the module to William within a week or so
  • William has tested the TI-node in master mode on the independent development board
    • The master mode is what Bryan would use to develop the CODA interface
    • This is the same version of the TI-node as what Bryerton has already integrated into the FPGA
  • Bryerton and Daryl need to have the TI slave connection demonstrated before we would produce more boards
    • Bryan will send information to Bryerton about what registers to set to put the TI-node into slave mode and how to tell if the TI-node is connecting properly to the master
  • Michael reports that the replacement amplifier chip delivery has been delayed until the end of October. Daryl will modify two more of the prototype boards; one will go to Mainz and one will go to Dustin.
  • Michael also reports that the 40 Enclustra FPGA modules we'd need for all the modules have now been shipped.
• Bob, Michael, and Paul need to get together to finalize what firmware modes we're requesting from Bryerton
• We plan to keep these meetings at noon eastern on alternating Fridays. The next meeting will be 26 August.