IntegrationDaq 210908

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Meeting information

 Meeting time:  3:00pm Eastern
 
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Agenda

• Activity updates
  • Bob has sent drafts of requirements document and ICD to Paul; plan to circulate these early next week
  • Draft timing diagram: DocDB 790
• General discussion

Open Issues to be followed up later

1. Need two things by end of August (no hard deadline). Some of this is just cut/paste from existing docs.
   1. Design requirements document -- examples and template : http://userweb.jlab.org/~rom/mollerdaq/design
   2. ICD -- interface control document(s). -- apparently Robin Wines made a template and it's on sharepoint. It seems we need several of these (infrastructure to DAQ; detectors to DAQ, etc).
2. Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
3. Create a timing diagram showing the integration gates in the injector and hall, helicity transitions, etc.

Minutes

Recording on Bluejeans.com: [1]

Absent: M. Gericke, C. Cuevas, B. Shaw, D. Bishop

Participants: B. Moffit, P. King, W. Gu, J. Fast, R. Michaels, B. Blaikie, J. Pan

• Discussion of the timing diagram
  • Bryan says that the "busy" ought to be based on whether the front-end modules have enough space to store another event, so the system busy I was thinking about doesn't really make sense.
    • A late thought I had: if a module has been programed to take too many samples, it may be still trying to complete the previous integration when a new window begins. What will be our means of determining if that is happening?
  • Question about the various clocks; do we need to specifically synchronize the ADC sample clock with the helicity gate?
    • We had previously determined that we only needed to synchronize the gate to about 100ns, which is about 2-3 of the samples. We don't have to have the ADC sample clock exactly starting at the beginning of the Tstable window.
    • However we wonder if it might be possible to synchronize the HelBoard clock to the DAQ clock; or to use the 20 MHz output from the HelBoard to synchronise the DAQ clock.
  • Paul asks if the ~19 microsecond delay between the arrival of the trigger at the TI and the desired start of the integration gate will be a problem. William says that right now the TI doesn't support such long delays, but it should be possible to change it.
• Requirements and ICDs: We plan to circulate a draft to the two DAQ working groups and the relevant CAMs on ~13 September. The deadline is ~19 September.
• Jie reports that the PCB bare board fabrication is done and the vendor is doing tests. All of the components needed to complete the five prototype boards have been sent to the vendor.
• Brynne reports that she's been doing tests with the 2-channel prototype, and is starting to prepare for the October beam tests in Mainz