IntegrationDaq 240419

Meeting information

 Meeting time:  1:00pm Eastern
 
 Zoom connection information is sent out by email; please reach out to Paul if you don't have the current link.

Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
Draft timing diagram: DocDB 790
Michael, Bob, Brynne, and Paul should put together a list of the integrator running modes we would like to have available

Recording at zoomgov:

Participants: R. Michaels, P. King, R. Conaway, S. Chatterjee, D. Bishop, B. Blaikie, A. Sen, J. Pan, H. Liu, D. McNulty, M. Gericke, B Shaw

Status of the specification document
- Bryerton recommends that the FPGA should accumulate based on 64-bit words, and the CODA process would truncate tp the low-32 bits for the production data stream.
- We still need to finish the discussion about the "latency synchronization" request. Paul expects to get a draft circulated to Bryerton/Michael/etc within the next few weeks
Brynne doesn't have the full results yet, but shows some preliminary results
- Leakage from -32.2e3 ppm in one channel into a DC voltage on the next gives ~50 ppb but the leakage asym is about 2stddev from zero (uncertainties on the leakage asyms are about 20ppb).
- Adding the shielding boxes over the input circuits makes only a very modest reduction in the leakage asym.
- Two of the boards have a much noisier result on channel six. It is not yet clear what is going on there
  - Bryerton has a test for Brynne to try running to check the ADC timing
Bryerton reports that the SFP port on the board now is working
Daryl asks us to get the specification document finished up, as he and Bryerton are getting some pressure to finish the development project
- TRIUMF management asked him to wrap up the project in the next quarter.
Discussion of the QSFP data link
- Will the switch use 10G SFP or would it expect the QSFP connection from the ADC?
What tests can we do to show that the TI section is working properly? When could those happen.