IntegrationDaq 210409

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Meeting information

 Meeting time:  3:30pm Eastern
 
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Agenda

• Activity updates
• Further discussion of the 60% review: DocDB 709
• Test-stand planning
• General discussion
  • Next meeting would be 23 April; should we cancel due to the collaboration-wide "forum" on 21 April?

Minutes

Recording on Bluejeans.com: [1]

Participants: B. Shaw, D. Bishop, M. Gericke, R. Michaels, W. Gu, P. King

• Discussion of the 60% review recommendations & comments
  • We will want to test the trigger/clock distribution with the TI-bridge module. I (Paul) thinks that Bryan is starting to work with the TI-bridge
    • Daryl asks which of the TI connections need to be sent back from the ADC module. William suggests that the RX0/TX0 (trigger) should be send back. The RX1 (clock) and RX2 (sync) don't need to be send back. The RX3/TX3 should be a hard loopback; it doesn't need to go through the FPGA.
  • Comment about scrubbing techniques to mitigate Single Event Upsets
    • Daryl suggests that some FPGA have a hardware bit indicating that there's a problem. Daryl will check if the Xylinx supports ECC DRAM
    • Michael and Bob make the point that we would want to have the shielding of the main bunker such that SEU are very rare.
    • We should also have both the subblock values and the full-event values for each channel to allow us to verify the sum or the subblocks matches the full-event
  • HVMAPS support in CODA: the current concept is that the HVMAPS would be readout through the same FPGA board as we're using for the integrating ADCs, so the CODA development work will be directly applicable
    • Michael reports that there is a board being produced at CERN in large quantities between the Ultrascale FPGA and the HVMAPS. He'll check on what would be involved in purchasing those
  • Power supply for the modules should be discussed with JLab Electrical Safety folks. The plan would be to use rack-mount power supplies to supply the low voltages to the ADC modules. The ones Michael has looked at are floating, so those would need to be discussed
• Talking about test stands
  • Paul presented a concept of a test stand needed to do tests with the trigger distribution
  • Bob suggests that we discuss who are planning to do which sort of tests, and what test-stand equipment are needed for those tests.
  • Daryl asks if they could get a TI board, either VME or pcie. This would be to provide a source to test the TI connection on the ADC. Bob will look into this
• Activity updates
  • Daryl is working on the board layout and expects to be done in 2-3 weeks
    • Michael asks if we're sure that we've decided to use the XU1 SOM. Daryl says that yes, that SOM has enough of the high performance pins to communicate with the ADCs.
  • Michael reports that they have two test stands set up, one for the counting mode evaluaiton of detector prototypes, and one for the integrating ADC prototypes
    • Brynne and Jie will start doing tests of the noise behavior with the new switching base