CountingDaq 210217

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Meeting information

 Meeting time:  3:00pm Eastern
   
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Agenda

• Discussion of preliminary design document
• What we need to do before the preliminary design review?
  • Cabling and crate layouts
  • FPGA trigger concepts
  • Event data structure
  • Data and event rate estimation
  • What are the requirements and the interfaces to other subsystems
  • Grounding and shielding
  • What are our requirements for deadtime, trigger rate, etc
  • What else do we need to define?
• General discussion

Minutes

Participants: B. Moffit, C. Ghosh, D. Armstrong, R. Michaels, J Fast, H. Liu, P. King

• Discussion of the preliminary design document
  • David expects that we would be using a Phillips Scientific x10 amplifier, such as the PS776. [The PS776 has 16 channels per module, and each channel has a non-inverting voltage gain of 10 and operates from DC to over 275 MHz]
  • fADC250
    • We think that we only need a few ns timing resolution, and for that using the fADC without the VETROC would work
      • Bryan noted that the JLab discriminator/scaler module may be built on a 125 MHz clock, and they may not have an analog threshold crossing at all. IN that case, they would give us a 8 ns jitter on the timing and triggering. He will follow up if he is recalling that correctly.
    • It has has three full scale ranges that are set by hardware jumper for each channel individually: full-scale of -0.5V, -1.0V, or -2V.
    • Each channel has an independent threshold, and the sample in which the threshold crossing occurs can be sent to the VTP as the trigger source. This will give a trigger jitter of about 4ns, due to the fADC250 sample clock
    • With a firmware change, it is possible to have positive voltage inputs instead of negative voltages. The thresholds would work the way you'd expect: indicating voltage moving away from zero
    • The fADC has internal scalers for the threshold crossings. They can be readout in the data stream, or can be accessed independently
    • Would we want to use the raw mode (all samples in the window) or an integral mode? Probably at least some data would be taken in raw mode
    • What integration widow is enough to capture the full pulses?
      • Chandan showed us scope pictures form the PREX quartz detectors that returned to baseline in 80-120 ns.
      • He also found a scope trace from Michael's PMT tests that similarly required ~80 ns to contain the peak.
  • David asks if we can get the small angle monitors (in current mode) into the counting mode readout
    • Maybe include one of the integrating ADCs in the couting mode DAQ?
    • Or maybe shift the small angle monitor signals after the transimpedance amp into one of the fADC channels?
  • Raster: Jim points out that the raster rework is being done this year, so if we want to have input into the new system (and the pickoff) we should get in touch with C. Cuevas
• David and Hanjie will discuss possible trigger configurations with the optics group at their meeting next week