Difference between revisions of "IntegrationDaq 230113"
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Back to [[Main_Page|Main Page]] >> [[DAQ Meetings|Data Acquisition Meetings]] >> [[DAQ Meetings#Integrating mode DAQ meetings|Integrating mode DAQ meetings]] | Back to [[Main_Page|Main Page]] >> [[DAQ Meetings|Data Acquisition Meetings]] >> [[DAQ Meetings#Integrating mode DAQ meetings|Integrating mode DAQ meetings]] | ||
| − | [[IntegrationDaq_221216 | previous meeting]] << >> [[ | + | [[IntegrationDaq_221216 | previous meeting]] << >> [[IntegrationDaq_230127 | following meeting]] |
== Meeting information == | == Meeting information == | ||
| Line 18: | Line 18: | ||
== Agenda == | == Agenda == | ||
* Activity updates | * Activity updates | ||
| + | ** Bryerton: Quick notes on the TI test | ||
| + | *** Verified all signals were locked to clock, with no apparent jitter | ||
| + | *** Signal from genoutp verilog array used appears to be SYNC signal (the purple signal). Could not get 'trigger' signal to appear on digitizer side | ||
| + | *** PCIe card signal shown is from 3rd pair on TIpcie card (the yellow signal) | ||
| + | *** Commands used to move SYNC signal from zero to full scale range on digitizer module:<br/>devmem 0x80000050 32 0x00000000 (712ns before of sync from TIpcie)<br />devmem 0x80000050 32 0x0000FF00 (312ns after sync from TIpcie) | ||
| + | *** Command used for screenshots<br />devmem 0x80000050 32 0x0000B600 (sync inside trigger window)<br />devmem 0x80000050 32 0x0000FF00 (sync outside trigger window, post-trigger window) | ||
| + | *** DIP position from pin 1 to pin 6: 100010 | ||
* General discussion | * General discussion | ||
Latest revision as of 21:53, 26 January 2023
Back to Main Page >> Data Acquisition Meetings >> Integrating mode DAQ meetings
previous meeting << >> following meeting
Meeting information
Meeting time: 12:00pm Eastern Zoom connection information Join ZoomGov Meeting https://jlab-org.zoomgov.com/j/1603800887?pwd=aXVmSnN6aWZWN3RBdXB4RUhGckZJdz09 Meeting ID: 160 380 0887 Passcode: 903612 US Tool free phone: (833) 568 8864 Find your local number: https://jlab-org.zoomgov.com/u/ab8341cjcG
Agenda
- Activity updates
- Bryerton: Quick notes on the TI test
- Verified all signals were locked to clock, with no apparent jitter
- Signal from genoutp verilog array used appears to be SYNC signal (the purple signal). Could not get 'trigger' signal to appear on digitizer side
- PCIe card signal shown is from 3rd pair on TIpcie card (the yellow signal)
- Commands used to move SYNC signal from zero to full scale range on digitizer module:
devmem 0x80000050 32 0x00000000 (712ns before of sync from TIpcie)
devmem 0x80000050 32 0x0000FF00 (312ns after sync from TIpcie) - Command used for screenshots
devmem 0x80000050 32 0x0000B600 (sync inside trigger window)
devmem 0x80000050 32 0x0000FF00 (sync outside trigger window, post-trigger window) - DIP position from pin 1 to pin 6: 100010
- Bryerton: Quick notes on the TI test
- General discussion
Open Issues to be followed up later
- Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
- Draft timing diagram: DocDB 790
- Michael, Bob, Brynne, and Paul should put together a list of the integrator running modes we would like to have available
Minutes
Recording at zoomgov:
Participants:
