Difference between revisions of "IntegrationDaq 211103"

Latest revision as of 19:40, 4 November 2021

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Meeting information

 Meeting time:  3:00pm Eastern
 
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Agenda

• Activity updates
• General discussion
  • Instrumenting BPMs & raster signals: other experiments use in-line attenuators and we can do that for signals that don't fit into the 50ohm single-ended range of +/-4V
  • Discussion of possible use of Mainz dual mode amplifier design in the front-end

Open Issues to be followed up later

1. Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
2. Draft timing diagram: DocDB 790

Minutes

Recording on Bluejeans.com: [1]

Participants: B. Moffit, W. Gu, P. King, D. Bishop, J. Pan, B. Blaikie, M. Gericke, B. Shaw, R. Michaels, J. Fast

• Activity updates
  • Michael: Doesn't have a summary of the Mainz test beam dats yet. It went well; he hopes to have something ready to discuss next meeting.
  • Bryerton: He's recieved the 16-ch boards. He has been able to power it up over PoE and talk to the FPGA.
  • Daryl: He has ordered loopbacks for the QSFP to be able to do the IBERT tests
• Discussion about 10Gbit/s links from the integrating ADC module
  • Daryl reports that the 10Gbit/s IP from Xilinx is very expensive (~20k $US) and that TRIUMF doesn't have it
  • William thinks that we could check with Ben Raydo if JLab does have it
  • Do we need 10Gbit/s or is 1Gbit/s enough?
    • Michael would want to be able to have a continuous 1 second at the full sample rate to be able to do Fourier transformations down to few Hz frequencies.
    • One channel would be roughly 400Mbit/s (previous estimate was 34MB/ch/s ==> 272Mbit/ch/s; exact data rate will depend how we pack the data). If we want to be able to do this for more than one channel in a module at once, we'd need the 10Gbit/s connection. Assuming the rest of our networking/computing could support that. And if we're doing this for multiple modules it will further stress the networking/computing.
• Plans for firmware development
  • Bryerton probably has a few weeks of work to port the 2-ch firmware to the 16-ch board.
  • Once that firmware is available, Michael would want to test all the channels on a board before sending one out
  • Daryl thinks they wouldn't be able to get to the TI code until January (Bryerton will be out for most of December)
    • Bryerton asks if there is a stripped down module for the TI code
      • William had some issue with putting the firmware up on github; Bryan and he will follow up offline about that
    • Michael suggests that maybe once the 2-ch firmware had been ported, they could send William a board and he could add the TI firmware as the first TI-supported version. There's some discussion back and forth about this idea.
  • Bryerton will report on his progress at the next meeting, and then we can discuss how to proceed from there.