View source for IntegrationDaq 240614

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== Meeting information ==
  '''Meeting time:'''  1:00pm Eastern
  
  Zoom connection information is sent out by email; please reach out to Paul if you don't have the current link.

== Agenda ==
*  Activity updates
*  General discussion

=== Open Issues to be followed up later ===
# Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
# Draft timing diagram: [https://moller.jlab.org/cgi-bin/DocDB/public/ShowDocument?docid=790 DocDB 790]
# Michael, Bob, Brynne, and Paul should put together a list of the integrator running modes we would like to have available

== Minutes ==
Recording at zoomgov:  

Participants:  P. King, B. Moffit, K. Dehmelt, R. Michaels, M. Gericke, S. Regmi, S. Chatterjee, A. Sen, B. Blaikie, W. Gu, J. Dutta, J. Pan, H. Liu, D. Bishop, D. McNulty, S. Kundu

*  I need to take the discussions from last meeting and update the specification document, and then we need to discuss it with Bryerton
*  Bryan:  they have the two rev1 boards connected to a single TI module
**  They can verify that the MOLLER-TI node is receiving the 250MHz clock
**  They can send triggers and syncs, but they are not being decoded properly in the MOLLER-TI node.
**  They can see in a register that they 
**  Bryan is able to access the TI registers in the node through the zmq 
**  Debugging is continuing
*  Brynne:  they are finishing testing the other ADC modules to be able to send the other modules out to the 
*  Michael:  we need to finish the specifications and especially the TI testing before going to the full production
*  Michael and Daryl discuss the possible change from QSFP to SFP+
**  This would be another change on the board, because we do have all four lanes connected from FPGA to the connector
**  Keeping the QSFP and using QSFP-to-SFP+ converters; these are approximately 50$ or so and would replace the 
**  If we wanted to use more than one lane of the QSFP, we'd need to implement it in the FPGA later
**  We'll keep the QFSP on the board and use QSFP-to-SFP+ adapters---Michael and Paul will discuss if the adapters will be part of the ADC deliverable or part of the "DAQ networking" deliverable
*  Bryan asks about the front panel "reset" input
**  Daryl says that it goes through an opto-isolator, so the exact signal type is pretty insensitive. More than 1V with a minimum 10 us should work