Digital BCM Meeting, 2021 January 21

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Meeting information

 Meeting time:  2:00pm Eastern
 
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Agenda

• Possible concept from last meeting
  • The idea of streaming data from the FPGA is something that is being developed for the JLab VTP, and recently entered consideration for our integrating ADCs
  • The trigger interface likely needs to be added to the digital BCM module for this to work like the VTP
• General discussion

Minutes

Participants: B. Moffit, Y. Mei, S. Li, R. Michaels, H. Liu, E. Sichtermann, Y. Kolomensky

• Bryan starts by saying that I (Paul) had misunderstood part of the discussion from the integrating ADC meeting I had paraphrased as the start of today's discussion. What Ben is developing for the VTPs requires not just a TI but also a ROC to handle the CODA control. The data does not need to flow through the ROC, however.
  • The device responsible for reading out the device needs to have an associated ROC process. The ROC does not need to handle the event data, but does need to be able to handle the CODA control events and to communicate the configuration to the data source.
  • In later discussion, Bryan thinks that the associated ROC process can be running in a physically separated CPU. This needs to be checked
• Yuan states that they are using evaluation board VCU108.
  • This board does not have a SOC. Changing the FPGA board is not something they'd want to do
• Discussion of objectives and options for having the BCM readout not going through the large server as shown in LBL BCM data stream.
  The end result of that discussion is the following concept:
  • The FPGA will have the TI functionality, and the QSFP on the evaluation board will be used for the TI connection.
    • The LBL folks will need to get the firmware blocks for the TI
  • The 1 Gbit port on the evaluation board will be used for both the configuration and event data transfer
    • The ROC process will run on a small Linux CPU; this may be enclosed within the chassis of the BCM module, or it may be a stand-alone unit. Bryan was not certain that while we do need a ROC process for each module, we may not need an independent CPU for each BCM chassis; it may be sufficient to have multiple processes on a central CPU.
    • The ROC process would be responsible for the slow control of the BCM module, including setting the destination for the data
    • The FPGA would handle building the event fragment and sending it over the network to the event builder. The data transfer would go through the 1 Gbit port on the evaluation board
• Bryan will be checking on the details of running a ROC and data transfer to the EB like this and will follow-up with us by email. We will not schedule a meeting yet