IntegrationDaq 220909

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Back to Main Page >> Data Acquisition Meetings >> Integrating mode DAQ meetings

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Meeting information

 Meeting time:  12:00pm Eastern
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Open Issues to be followed up later

  1. Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
  2. Draft timing diagram: DocDB 790
  3. Michael, Bob, Brynne, and Paul should put together a list of the integrator running modes we would like to have available


Recording at zoomgov: [1]

Participants: W. Gu, P. King, B. Moffit, R. Michaels, B. Blaikie, B. Shaw, J. Pan, C. Zorn, D. Bishop, D. McNulty, M. Gericke

  • Chassis for the integrating ADC
    • If the switch doesn't support PoE++, power can be supplied by a 48V supply (the input can actually be between 35V and 72V). The chassis needs ~28W of power.
    • The fans can be powered by an external supply as well. These are 12V fans.
    • Bryerton comments that he's surprised they took the fan off the heat sink; after the meeting, William shifted the fan on top of the heat sync
    • We don't need the CR1220 cell unless we want the realtime clock.
    • There are three fan connectors in the chassis, if we want to have a push-pull ventilation of the box in addition to the fan on the heat sync
    • There is a ground screw that connects the chassis to the ground. It was intended to screw through the chassis to the ground point. This ground is not the same as the ADC reference ground.
      • One set of lemo connectors in the back of the module has their ground on the reference ground, and so should not be touching the chassis.
    • Note that the labels on the board for the LVDS Reference Clock are swapped
    • There is a switch on the board to use the QSFP-TI as a second data QSFP instead.
  • Activity updates
    • Bryerton has not had a chance to test the TI interface yet
    • Daryl is working on replacing the front-end amplifiers with replacements from TI. If that doesn't work, he'd do the simple modification on the two modules for Mainz and for Dustin
    • Michael and Paul discuss a possible HVMAPs instrumentation
      • The VTRx chips will be a SFP fiber for each ring 5 tile, so we'd need to support 84 SFP fibers (21 QSFP).
      • The FPGA in the VTP is more powerful than what had been considered for the HVMAPs readout, so the idea of doing the readout through VTP seems like the way to go. We would need two VTP crates to be able to support the 84 SFP fibers.
      • Added after the meeting: Ben suggests using an an Arisa 7130-96L FPGA-enabled network switch to act as the data concentrator for all the HVMAPs chips. This would allow all 84 connections from the ring 5 HVMAPs and would be a 2U unit. Ben thinks that adding TI support to the 7130-96L should be relatively straightforward, and the switch ought to be able to run CODA.