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== Meeting information ==
  '''Meeting time:'''  12:00pm Eastern
  
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== Agenda ==
*  Activity updates
*  General discussion

=== Open Issues to be followed up later ===
# Discussions with M. Pitt & J. Musson to understand the beam monitor signals we'll be getting
# Draft timing diagram: [https://moller.jlab.org/cgi-bin/DocDB/public/ShowDocument?docid=790 DocDB 790]
# Michael, Bob, Brynne, and Paul should put together a list of the integrator running modes we would like to have available

== Minutes ==
Recording at zoomgov:  [https://jlab-org.zoomgov.com/rec/share/SuF2DQQ45w-H0JOIa0ycRXAvXvmrghGu6EnF8nIKvE1NhLFtH765_Lp_Y294XYH9.yJAMCMdLPw4YbEFJ?startTime=1650642623000]

Participants:  B. Moffit, W. Gu, B. Shaw, J. Pan, J. Fast, P. King, B. Blaikie, M. Gericke, D. McNulty, R. Michaels, C. Zorn

*  Michael:
**  He had been at TRIUMF working with Bryerton and Daryl this week, and now has one of the 16-channel boards with him at Manitoba.  It is working well, but there has been one hardware issue found
**  The amplifiers used in the front-end filter were replaced by a variant part that had a different gain than was intended; the net effect is a de-amplification of about a factor of 100.
***  Daryl has replaced the resistors/capacitors on the filter amps for the first four channels of Michael's board to recover a gain of ~1, but the filtering performance isn't as good
***  The filter performance can be seen in the waveform data, and can be filtered out in software for the upcoming beam tests
***  They have ordered some of the proper amplifiers, which should arrive in June or so.  Then Bryerton will change them on the other boards.
**  The firmware allows one channel to be readout at the full 14.7 MHz sampling, or two channels can be read out at half rate.
*  Bryerton
**  The next step is to do the eye test on the QSFP transcievers, then he'd start work on the TI firmware.  William will coordinate with him to get the latest TI formware
*  Discussion of setting up the OU/JLab test stand for the integrating ADC
**  I think we should have it at JLab initially, so that its easier if we need help from the DAQ group.  We'll plan to set up in the TEDF cubicles.
***  Dustin and Devi have cleared out their equipment from the cubicle next to Bob's test stand
**  What will we need in the TEDF?
***  The board can get power through POE (Bryerton says it needs to be at least POE+) or from an external power connector.  On the power connector it would be 30W in the voltage range 37-57V.
***  What else?  Would need a server, a TI connection, etc
**  I think to get the initial system set up in a CODA system it should be at JLab, other testing might be done there or at OU
*  Other discussion
**  Michael asks if having some of the components with very long backorder times will be a problem for doing the FDR (some parts we need are listed online with more than a year of backorder time)
***  Jim says that as long as we can order the parts but with a long delivery time, its is a schedule issue but isn't a design issue.  If the design could change dramatically because we can't get a compatable part, then we should have been able to identify those issues before going to the final design review.