Digital BCM Meeting, 2021 January 07

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Meeting information

 Meeting time:  2:00pm Eastern
 
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Agenda

• Control signal inputs: integrate gate or "start of integration"?
• Possible readout ideas
  • Each unit as stand-alone ROC similar to integrating ADCs
  • Units are read by a computer with TI-pcie running a PC-ROC
  • Units communicate with a VXS module (such as SSP) in a VXS-ROC
• Data structure; what is reported?
  • Integrating ADCs plan to have: sum over window, sum of squares (to calculate RMS within window), minimum sample value, maximum sample value; full window and four sub-blocks. Integrating ADCs would also have a waveform mode.
• General discussion
• LBL BCM data structure

Minutes

Attendees: Paul, Bob, Yuan, Yury, Ernst, Shujie

• Experiment requirements:
  • BCM info to integrating mode and counting mode DAQ
  • BPM info at low current (100 pA) for counting mode

• Proposed setup:
  • Integrate the BCM/server system to main CODA
  • Ideally, the FPGA on BCM will process the raw cavity signal (output at ~2kHz) and communicate with CODA (TODO: check with Bryan from DAQ group if both the ROC and TI can be implemented in the FPGA, or do we need a Unix shell for the ROC ) so that we can drop the server to increase system stability.
  • Helicity window signal (500us on, 10us off) to BCM.
    • is the helicity signal in sync with 10MHz clock? (very likely yes)
    • how to define the rising edge of helicity window (~50ns ??)
    • need to sync the helicity with BCM input signal. Use the LED delta signal to check sync?